/* add user code begin Header */ /** ************************************************************************** * @file at32f403a_407_wk_config.c * @brief work bench config program ************************************************************************** * Copyright (c) 2025, Artery Technology, All rights reserved. * * The software Board Support Package (BSP) that is made available to * download from Artery official website is the copyrighted work of Artery. * Artery authorizes customers to use, copy, and distribute the BSP * software and its related documentation for the purpose of design and * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. * ************************************************************************** */ /* add user code end Header */ #include "at32f403a_407_wk_config.h" /* private includes ----------------------------------------------------------*/ /* add user code begin private includes */ /* add user code end private includes */ /* private typedef -----------------------------------------------------------*/ /* add user code begin private typedef */ /* add user code end private typedef */ /* private define ------------------------------------------------------------*/ /* add user code begin private define */ /* add user code end private define */ /* private macro -------------------------------------------------------------*/ /* add user code begin private macro */ /* add user code end private macro */ /* private variables ---------------------------------------------------------*/ /* add user code begin private variables */ /* add user code end private variables */ /* private function prototypes --------------------------------------------*/ /* add user code begin function prototypes */ /* add user code end function prototypes */ /* private user code ---------------------------------------------------------*/ /* add user code begin 0 */ /* add user code end 0 */ /** * @brief system clock config program * @note the system clock is configured as follow: * system clock (sclk) = hick / 12 * pll_mult * system clock source = HICK_VALUE * - hext = HEXT_VALUE * - sclk = 240000000 * - ahbdiv = 1 * - ahbclk = 240000000 * - apb1div = 2 * - apb1clk = 120000000 * - apb2div = 2 * - apb2clk = 120000000 * - pll_mult = 60 * - pll_range = GT72MHZ (greater than 72 mhz) * @param none * @retval none */ void wk_system_clock_config(void) { /* reset crm */ crm_reset(); crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); /* enable battery powered domain access */ pwc_battery_powered_domain_access(TRUE); /* check lext enabled or not */ if(crm_flag_get(CRM_LEXT_STABLE_FLAG) == RESET) { crm_clock_source_enable(CRM_CLOCK_SOURCE_LEXT, TRUE); while(crm_flag_get(CRM_LEXT_STABLE_FLAG) == RESET) { } } /* disable battery powered domain access */ pwc_battery_powered_domain_access(FALSE); /* disable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, FALSE); /* enable hext */ crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ while(crm_hext_stable_wait() == ERROR) { } /* enable lick */ crm_clock_source_enable(CRM_CLOCK_SOURCE_LICK, TRUE); /* wait till lick is ready */ while(crm_flag_get(CRM_LICK_STABLE_FLAG) != SET) { } /* enable hick */ crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) { } /* config pll clock resource */ crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_30, CRM_PLL_OUTPUT_RANGE_GT72MHZ); /* enable pll */ crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); /* wait till pll is ready */ while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) { } /* config ahbclk */ crm_ahb_div_set(CRM_AHB_DIV_1); /* config apb2clk, the maximum frequency of APB2 clock is 120 MHz */ crm_apb2_div_set(CRM_APB2_DIV_2); /* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */ crm_apb1_div_set(CRM_APB1_DIV_2); /* enable auto step mode */ crm_auto_step_mode_enable(TRUE); /* select pll as system clock source */ crm_sysclk_switch(CRM_SCLK_PLL); /* wait till pll is used as system clock source */ while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) { } /* disable auto step mode */ crm_auto_step_mode_enable(FALSE); /* update system_core_clock global variable */ system_core_clock_update(); } /** * @brief config periph clock * @param none * @retval none */ void wk_periph_clock_config(void) { /* enable emac periph clock */ crm_periph_clock_enable(CRM_EMAC_PERIPH_CLOCK, TRUE); /* enable emactx periph clock */ crm_periph_clock_enable(CRM_EMACTX_PERIPH_CLOCK, TRUE); /* enable emacrx periph clock */ crm_periph_clock_enable(CRM_EMACRX_PERIPH_CLOCK, TRUE); /* enable emacptp periph clock */ crm_periph_clock_enable(CRM_EMACPTP_PERIPH_CLOCK, TRUE); /* enable iomux periph clock */ crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE); /* enable gpioa periph clock */ crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); /* enable gpiob periph clock */ crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); /* enable gpioc periph clock */ crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); /* enable gpiod periph clock */ crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE); /* enable uart7 periph clock */ crm_periph_clock_enable(CRM_UART7_PERIPH_CLOCK, TRUE); /* enable tmr13 periph clock */ crm_periph_clock_enable(CRM_TMR13_PERIPH_CLOCK, TRUE); /* enable uart5 periph clock */ crm_periph_clock_enable(CRM_UART5_PERIPH_CLOCK, TRUE); /* enable can1 periph clock */ crm_periph_clock_enable(CRM_CAN1_PERIPH_CLOCK, TRUE); /* enable can2 periph clock */ crm_periph_clock_enable(CRM_CAN2_PERIPH_CLOCK, TRUE); } /** * @brief nvic config * @param none * @retval none */ void wk_nvic_config(void) { nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0)); NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0)); // NVIC_SetPriority(UART7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));//emac = 5 nvic_irq_enable(EMAC_IRQn, 5, 0); } /* add user code begin 1 */ /* add user code end 1 */